1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit.
2. Description of the Prior Art
A PLL frequency synthesizer, known as a PLL circuit, which is currently available in mobile communications and other applications is shown in FIG. 4. A counter 42 divides a frequency of an output signal of a reference signal source 41 to produce an output signal indicative of a divided frequency signal of the reference signal source 41. Another counter 44 divides a frequency of an output signal of a voltage-controlled oscillator (VCO) circuit 43 to produce an output signal indicative of a divided frequency signal of the output signal from the voltage-controlled oscillator (VCO) circuit 43. A phase comparator circuit 45 compares these two output signals and produces output signals from its terminals UP and DN, respectively. These output signals have pulse widths corresponding to the amount of lag or lead of the phase of the output signal FV from the counter 44 with respect to the output signal FR from the counter 42. A charge pump 46 charges or discharges capacitive elements (not shown) in response to the output signals appearing at the terminals UP and DN. The charging current from the charge pump 46 is smoothed out by a low-pass filter 47. The output voltage signal from the filter 47 is supplied as a control voltage to the voltage-controlled oscillator circuit 43. Shifts of the phases of the output signals FR and FV introduced at a startup or when a channel is switched are fed as the control voltage back to the voltage-controlled oscillator circuit 43. As a result, the frequencies of the output signals FR and FV become coincident. That is, the PLL circuit locks up.
In the circuit shown in FIG. 4, the counters 42 and 44 do not start to count simultaneously. Therefore, the phase difference detected by the phase comparator circuit 45 does not agree with the actual phase difference between the output signals FR and FV. For example, it is assumed that the output signals FR and FV have periods of fR and fVl, respectively, in the initial state as illustrated in the timing chart of FIG. 5, and that the phase difference delivered from the phase comparator circuit 45 is .alpha.1. If the output signal FV subsequently assumes a period of fV2, a phase difference .alpha.2 delivered from the phase comparator circuit 45 at the next phase comparison timing is given by EQU .alpha.2=(fR-.alpha.1)-fV2
On the other hand, the actual phase difference .alpha.3 between the output signals FR and FV is given by EQU .alpha.3=fR-fV2
In this way, the phase difference .alpha.2 produced from the phase comparator circuit 45 is not coincident with the actual phase difference .alpha.3. Consequently, appropriate feedback control on the control voltage is not provided. This has prolonged the locking time.